On Feb 13, 2013, at 10:42 PM, David MacMahon wrote: > Unfortunately, the CASPER "Shared BRAM" block does not have a latency setting > (defaults to 1?) so the tools do not end up using the underlying BRAM's > optional output register (even if there is a register on the Shared BRAM's > output that could, in theory, be absorbed into the underlying BRAM).
I just built (using version 13.3 of the Xilinx tools) a test model that had a Xilinx SysGen BRAM block with Latency set to 1 and whose dout port was connected to a register block. After building the design and running a verbose timing report, I can see that the register was not "absorbed" (i.e. mapped) into the BRAM block. In fact, despite numerous attempts with various map options and manually resynthesizing things, I could never get a register on dout to be absorbed into a BRAM. The only way I could get the optional output register to be used was by setting the latency to 2 on the Xilinx BRAM block. That will help timing with Xilinx BRAM blocks, but it won't help at all with CASPER Shared BRAM blocks. I think the CASPER Shared BRAM blocks are woefully slow due to this. Dave
