I just loaded the latest version of tcpborphserver dated
2013-02-12T17:00:21 for my ROACH2. I've recompiled tutorial1 for a
ROACH2 and I'm able to load the bof file to the FPGA, however when I try
to read a register I get a communications error from the Roach and the
personality of the FPGA is dumped. The roach is still on the network
and KATCP is still there, but I have to reload the BOF file. It appears
I can write to registers correctly. If I request say 5 bytes from the
sys_stratchpad KATCP recovers gracefully with an error, but if I request
4 bytes I get the following error dump from the ROACH2, as read from the
USB serial interface:
Machine check in kernel mode.
Data Read PLB Error
Oops: Machine check, sig: 7 [#6]
PowerPC 44x Platform
Modules linked in:
NIP: 10004ff8 LR: 10004fcc CTR: 1000547c
REGS: efbcdf10 TRAP: 0214 Tainted: G D W (3.4.0-rc3+)
MSR: 0002f900 <CE,EE,PR,FP,ME> CR: 42002424 XER: 0000005f
TASK = efbd4100[489] 'tcpborphserver3' THREAD: efbcc000
GPR00: 00000000 bfc7faf0 48021c60 00000000 00000000 00000000 10045fbc
00000000
GPR08: 00000000 4802a00c 00000000 bfc7faf0 22002422 100598dc 00000000
00000000
GPR16: 1ff6b47c 1ff62098 00000000 00000000 00000000 00000000 00000000
bf8b8fae
GPR24: 100028c4 100450a8 00000008 48028e64 00000000 00000004 1005808c
bfc7faf0
NIP [10004ff8] 0x10004ff8
LR [10004fcc] 0x10004fcc
Call Trace:
---[ end trace 9a1ad1718c70baa4 ]---
roach VMA close
roach release mem calledBus error
root: tcpborphserver exited with code 0
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x18, len=1
i2c i2c-0: master_xfer[1] R, addr=0x18, len=1
i2c i2c-0: master_xfer[0] W, addr=0x4c, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4c, len=2
i2c i2c-0: master_xfer[0] W, addr=0x4c, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4c, len=1
i2c i2c-0: master_xfer[0] W, addr=0x4c, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4c, len=1
i2c i2c-0: master_xfer[0] W, addr=0x4e, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4e, len=2
i2c i2c-0: master_xfer[0] W, addr=0x4e, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4e, len=1
i2c i2c-0: master_xfer[0] W, addr=0x4e, len=1
i2c i2c-0: master_xfer[1] R, addr=0x4e, len=1
