Hi Louis,
I have the same problem of "roach & adc sampling rate". We want to use ROACH as a holography correlator,but the sampling frequency is too high. After we reset the MSSGE block clock rate to 50 MHz, and also used the method you have been used(change all of the instances of 'HIGH' to 'LOW'in the file of XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd), but the bee_xps always complain a error. The ADC we used is a 2*1000-8 one. The ADC sampling rate we want to use is 80MHz, so the FPGA clock is 20MHz. Is there any lower limit for the ROACH clock rate?(same question) Best, Peixin -- ========================================== 裴鑫 (Xin Pei) 中国科学院新疆天文台 Xinjiang Astronomical Observatory, CAS 新疆乌鲁木齐市科学一街150号 (邮编: 830011) 150, Science 1-Street Urumqi, Xinjiang 830011 China 电话(Tel): +86-(0)991-3689068 传真(Fax): +86-(0)991-3838628 ==========================================
