On 10 June 2013 17:07, David Saroff <dsar...@nrao.edu> wrote: > Short of compiling a design, can the resource usage of a PFB yellow block > be seen?
> If the data rate is some submultiple of the FPGA clock, say 50 MSPS and > 200 MHz is there a natural way to share resources? > > The question's context: > 38 dipole antennae of the focal plane array for the green bank telescope. > Signal from each of the 38 is sampled at 50 MSPS, digitized to 12 bits. > What frequency resolution fits on a virtex-6? That is what is the number > of taps P and fft bins n that will fit? > > Count multipliers as dsp48 blocks. > > 2000/38 =~ 50 dsp48 blocks per signal. That doesn't seem like enough. If > there is a way to resource share, is there a factor of 200MHz/50MHz = 4 > available ideally? Since I think you're talking about using the 64 input ADC, this is the default input format. I.e, the 64x50MSa/s channels are presented to the FPGA as 16x200MSa/s streams. There is a version of the CASPER PFB-FIR block designed to deal with this, and with appropriate reordering, a normal CASPER FFT works too. > Then it looks more like 4 * 50 = 200 dsp48's per > channel. That still doesn't seem like enough. This is actually quite a lot. A PFB only costs 1 multiplier per tap per stream, and an FFT costs scales only with log(N) > > What about a sample rate of 2.5 MHz? Then the potential reuse multiplier > is 200MHz/2.5MHz = 80 and the number of multiplies per channel is a more > comfortable 80 * 50 = 4000 The bandwidth is less for the 2.5 MSPS vrs 50 > MSPS, by a factor of 1/20th. That makes fewer fft bins n necessary, so > might the advantage of lower sampling rates and narrower band widths be > quadratic? > > Summary > 1)when we parametrize a PFB, can we conveniently see how many dsp48s and > slices, etc it requires? > As a rule of thumb the PFB FIR will cost you one multiplier per tap, and the FFT ~2log(N) (where the 2 is from 4 multipliers per complex mult / 2 real streams FFT'd as one complex). [I'm sure someone will correct me if this isn't right] Rurik wrote a nice memo about PFB utilization (though geared towards wide bandwidth implementation): https://www.cfa.harvard.edu/twiki/pub/SMAwideband/MemoSeries/sma_wideband_utilization_1.pdf > 2)if a PFB receives samples slower than the system clock, is there a way > to share it between channels? > I don't know what the capabilities of Xilinx libraries are, but with the 64-input ADC we have been using a slightly modified version of the PFB block (https://github.com/oxfork/mlib_devel/tree/master/ox_library) which accepts time multiplexed data streams. We then reorder and use the normal CASPER FFT. FWIW, with this setup we can comfortably do 4-taps, 1024 channels (2048 pt FFTs) with 32 antennas on ROACH 1. We run out or RAM long before multipliers. Cheers, Jack > > some embarrassment for the beginner's questions. > > > > >
