Hi Dan, Could you also describe the adc schematic and the outputs (a0 - a16) for the asiaa_sinica_5g casper block? We are having a 1:1 demux adc, for which we are using only one input as of now. I am assuming that the adc will give 4 parallel samples (8-bit each) that could be used for further processing. However, choosing demux 1:1 draws the circuit with 8 outputs for each adc input. Which (and how many) outputs from the block does the samples correspond to?
Regards, Sarfraz On Wed, Jul 10, 2013 at 1:22 AM, Dan Werthimer <[email protected]>wrote: > > i suggest you try putting in a sine wave or a noise source > into the adc. > > the fpga clock is derived from the adc clock. > the adc divides it's clock by 2^k, and that signal is > fed to the fpga. > > it's pretty easy to achieve fpga designs to clock > at 200 MHz without much work. but if the fpga is > very full, this can be difficult. > experts can get the fpga to clock at 375 to 400 MHz, > but this requires knowledge of plan ahead.... > > best wishes, > > dan > > > On Tue, Jul 9, 2013 at 12:40 PM, Sarfraz Qureshi < > [email protected]> wrote: > >> Hi everyone, >> >> Tutorial 3's spectrum seems to be collecting unknown harmonics from >> somewhere. Attached images show full (/zoomed) spectrum for a 2048 channel >> 400MHz BW spectrometer programmed on R2 V2 with asiaa_sinica_5g adc with >> the adc input left open. Design 1 excluded the use of latency blocks in the >> model file but design-2 did use latency between two blocks for sync inputs. >> ADC is clocked at 800MHz. >> >> Is this a resultant of clock (fpga) harmonics? Besides, how is the fpga >> clock rate controlled/determined when the adc clock is used as a reference? >> In particular, when adc is clocked externally at 800MHz then what >> determines the clock rate of the fpga to be 200MHz? Also how fast could the >> fpga be clocked? >> >> Regards, >> >> Sarfraz Qureshi, >> >> IIT Indore >> > >
