hi xuexiu, there are 40 LVDS pairs on each zdoc connector. there are two zdoc's on roach1 (roach 2 also has two zdocs).
for roach1, you can get up to about 800 Mbit/sec per ZDOC LVDS pair with a -1 speed grade fpga. you can probably get up to 1Gbit/sec per LVDS pair if you use a -2 speed grade FPGA. see the xilinx virtex5 data sheet for max LVDS data rate. i'm not sure of the exact numbers. for roach2, you can get 1.2 Gbit/sec per ZDOC pair with a -1 speed grade part. see xilinx virtex6 data sheet for exact numbers. we typically bring the samples in at quad data rate (four adc samples per fpga clock, so 1Gbit/sec goes to four flip flips in the IO block of the fgpa and emerges as four bits at 250 Msamples/sec that go into the fabric of the fpga_. see some of the adc yellow interface blocks as an example of quad data rate (QDR)> and double date rate (DDR) fpga input codes. best wishes, dan On Fri, Jul 12, 2013 at 2:34 PM, Xuexiu Han <[email protected]> wrote: > Dear casper list, > > I'm a research student at University of Michigan working on Roach board > now. I want to connect our own high speed ADC (~1Gsps) to Roach1 board and > use it as a high speed logic analyzer. I wonder if you can help me on some > questions. > > 1. My ADC board doesn't demux itself, i.e. it outputs 1GHz clock and 8-bit > samples. Do ZDOK pins accept 1GHz clock (what frequency can these pins go > up to)? Should I use the built-in gpio block (with I/O group of ZDOK0) or > make a new yellow adc block? > > 2. I know FPGA virtex 5 has a global clock limit of 550 MHz. Is it > doablethat I deserialize the clock input and data input in Roach board > (after the data and clock goes through ZDOK connector) ? > > Thank you very much. > > Sincerely, > Xuexiu Han > >
