hi xuexiu, some of the adc yellow blocks implement a 4:1 demux (eg: data comes in from the adc at 1 Gbit/sec per lane, and data emerges from the yellow block at 250 MHz, but four times wider),
and some of the adc yellow blocks implement a 2:1 demux. and some of the adc yellow blocks do not implement any demux (no rate change). (data comes in at 250 Msps, and the FPGA is clocked at 250 Msps). in your case, where the data comes in at rates up to 1Gbit/sec per lane, i suggest you implement a 4:1 demux inside the FPGA I/O blocks, so the FPGA fabric clocks at 250 MHz. best wishes, dan On Tue, Jul 16, 2013 at 11:09 AM, Xuexiu Han <[email protected]> wrote: > Hi all, > > I wonder if the adc yellow blocks in simulink implement the on-chip demux > of adc data, i.e. the adc yellow blocks only serve as a 2:1 demux of zdok > input data using DDR at fpga side regardless of what has already been done > on adc board. > > If I want the ddr only at fpga to use another 8-bit adc, should I just > modify the ext_ports in xps_adc.m file and it's done? > > Thank you. > > Xuexiu >
