might be an adc problem. you could try swapping adc's. the adc outputs a clock using an LVDS pair. if one of the two clock traces were broken or shorted on the adc board, or on the fpga board, or in the zdoc connector, you might get some ringing on the differential pair (it wouldn't be terminated in 100 ohms and you'd only have half the signal going into the fpga) and this might lead to doubling the clock.
dan On Wed, Jul 17, 2013 at 1:03 PM, Nimish Sane <[email protected]> wrote: > Hi > > We are having an issue with one of the ROACH2 boards. We are programming > two different ROACH2s with the same bof file. Both have their ADCs clocked > by the signal derived from the same source. The ADC clock is 800 MHz, and > FPGA clock must be 200 MHz. > > However, we find that on one of the boards, FPGA clock frequency is > sometimes 400 MHz (confirmed from est_brd_clk() ). If we recycle the power, > the problem sometimes disappears, and it clocks correctly at 200 MHz. The > other board always clocks at 200 MHz without any issues. > > Does anyone have an idea what could be going wrong? > > Thanks, > > Nimish >
