Hi Rurik
I tried the recent changes to Shared BRAM on ska-sa but I ran into an
error during Update Diagram in munge_init.m resulting from commit
2c13dab where it's trying to index div_size which is just a integer.
Thanks for the fix :)
I
attach a patch which fixes this issue; however I'm now running into
another error during the Design Rules Check:
Problem with block: adc5g_test_slow/hist_0/count_a
: The gateway :
adc5g_test_slow/hist_0/count_a/adc5g_test_slow_hist_0_count_a_addr is
not preceded by a Xilinx converter block as it should be.
Where count_a is a Shared BRAM block. If I understand correctly the
toolflow uses convert blocks preceding gateway out blocks to determine
the port attributes for the top level netlist. Perhaps these were
removed for Shared BRAM in the effort to support other data types?
I plead ignorance (and stupidity for attempt at a quick fix) :-/ Thanks
for checking up on me.
Fix in ska-sa repo, simulated and compiled.
Regards
Andrew
