Comments below.
On Wed, Jul 24, 2013 at 12:07 PM, Matthew Bridges < matthewbridge...@gmail.com> wrote: > Hi JP and Wes, > > I am very interested in this work, but from a RHINO perspective. I am > looking into how I should go about adding the RHINOs DRAM into my > Architecture. > > I have a few questions, if you have time to answer. > > Did you use the Memory Interface Generator? And did it work for you? > Yes, use the MIG. Both R1 and now R2 yellow blocks are based around MIG > Are there other coregens used in your block? E.g FIFOs? > Yes, the outputted data goes though an asynchronous fifo. > How many ports did you implement? I was thinking of putting 2 into my > Architecture, 1 for the Wishbone, 1 for direct processor access. > What interface do you use to talk to the block? Is it OPB? > Both the QDR and DDR use a single "port" which maps the memory address space to OPB bus so that the memory can be read from the PPC. > > Thanks, > > Matthew > > > On Wed, Jul 24, 2013 at 11:48 AM, Wesley New <wes...@ska.ac.za> wrote: > >> This is great work JP. >> >> Out of interest is anyone else planning to use the DDR3 on ROACH2? >> >> Wesley New >> South African SKA Project >> +2721 506 7365 >> www.ska.ac.za >> >> >> >> >> On Wed, Jul 24, 2013 at 8:24 AM, Juan-Pierre Jansen van Rensburg < >> jvrensburg...@gmail.com> wrote: >> >>> Hi all >>> >>> I have been working on a yellow block for the DDR3 of the ROACH-2. As >>> far as I know this yellow block does not yet exist? >>> >>> >>> The same DRAM yellow block is used and interfacing the memory remains >>> the same (as for the ROACH-1). The DRAM also uses an asynchronous fifo to >>> allow long write bursts. I have tested the memory (thoroughly) using >>> standard memory test patterns, and the memory passes reliably (I have yet >>> to see a failure). >>> >>> I have not yet implemented a CPU interface to the DDR3, but this will >>> hopefully be done soon. I have a couple more things that I would like to >>> check/test, and if this is done I'll ask one of the SKA-SA guys to push >>> this onto their CASPER mlib git repo. >>> >>> I thought this is information worth sharing so that multiple people >>> don't end up working on the same thing... Hopefully this is not already the >>> case! >>> >>> Thanks, >>> JP van Rensburg >>> >>> >>> >>> >> > > > -- > Software Defined Radio Group > Department of Electrical Engineering > University of Cape Town > Private Bag X3, Rondebosch 7701 > Tell: +27 (0)21 650 4659 > Mob: +27 (0)84 413 2642 > >
