Hi, Henno, Thanks for the reply.
On Aug 1, 2013, at 12:50 AM, Henno Kriel wrote: > The IODELAY_CTRL block need to be clocked at 200MHz +/- 10MHz. From the > datasheet it is not clear whether you can clock the IODELAY block at a > different frequency - it just states that the average tap delay at 200MHz is > 78ps. Yes, the IODELAYCTRL element must be clocked at 200 MHz +/- 10 MHz, but I think that's separate and distinct from the IODELAY's clock input C. Page 98 of "Virtex-6 FPGA SelectIO Resources User Guide UG361 (v1.3) August 16, 2010" mentions that the IODELAY's clock input C "should be connected to the same clock in the SelectIO logic resources (when using ISERDES and OSERDES, C is connected to CLKDIV).". This implies that this clock input C is very independent from the IODELAYCTRL clock, so there is no FPGA limitation/constraint that would prevent the use of sys_clk here instead of sys_clk2x. Whether the qdr_controller will work that way remains to be seen. > I'm not sure what the effect would be if you clocked it at 100MHz, but let us > know what your experience is. I'll let you know! Thanks again, Dave
