Hey CASPER,
I've been working with some designs which have an obnoxious number of
yellow blocks, and the compile times are considerable (there was a
thread about this and caching netlists earlier).
If you're just updating some of your <black boxes> but not changing any
yellow-blocks, you can actually do the following to recompile your
design without re-synthesizing all of those yellow blocks:
(initial state: run through EDK/ISE/Bitgen at least once)
1. For each core which is being revised, click Generate on XSG
2. Copy the revised cores to XPS_ROACH_BASE/pcores
3. Check that they are, indeed, revised ("ls -ltrh")
4. Navigate to XPS_ROACH_BASE/implementation
5. "rm system.bld system.ngc system.ncd system.bit system.par"
6. Run EDK/ISE/Bitgen on casper_xps
7. Thank me for giving you an hour of your life back
I tried this for the user_ip core (the main one which has everything
which isn't in a pcore/<black box>), but it seems like it's synthesized
into a wrapper earlier, and thus you can't do this trick on it Maybe
some enterprising casperite can refactor the code to make it possible.....
--
--Ryan Monroe
626.773.0805
