Hi Guys, Thanks - I'm initially going to pursue the mmap option. I think quite a few of the issues are tcp latencies and by removing those I can make the link more reliable. I'm looking at a max of about 5Mb/s through the FPGA-->PPC interface. I should fairly soon be able to check what speed I can achieve.
Ross On Wed, Oct 16, 2013 at 11:26 AM, David Hawkins <[email protected]> wrote: > Hi Dave, > > >>> Boot the board, stop in U-Boot, write to the DMA registers >>> directly, and probe the bus to see what the maximum rate possible >>> is ... then you can decide whether to write a device driver to use >>> the DMA controller under Linux. >> >> >> Oh, yeah, trying to use the DMA controllers on the PPC side would be >> very interesting! I was referring to the CASPER implementation of >> the FPGA side of the EPB bus not supporting being a DMA bus master >> (I'm not even sure that the EPB bus supports external DMA bus >> masters). > > > The 440EP and the Freescale processors do not support external > DMA masters ... in fact, I'm not sure that I have seen any > recent processor that supports this feature (I've looked at > many ARM-based processor data sheets). Although I think its > a common feature on DSP processors ... > > >>> If Ross has never had to do this before, he might not have >>> appreciated where to look/where to start. >> >> >> If Ross has never had to do this before, he's probably better off >> using the pre-canned "Ethernet directly from the FPGA" solution >> rather than (re-)writing a Linux device driver to use DMA. :-) > > > Sure, I was just adding to his list of options :) > > Cheers, > Dave > > -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
