Hello Mark, Glenn, et al.,
Does anyone know of any CASPER FFT block that will take as inputs two
real sampled values (per ADC input) and output a single complex-valued
frequency bin per FPGA clock? The three FFT blocks that I’ve found on the
CASPER block documentation and the latest mlib library (wideband real, biplex
real 4x, and the biplex real 2x) all accept real sampled values but require a
minimum of 4 simultaneous values per FPGA clock per ADC input. I could really
use an FFT block (and a corresponding polyphase FIR block) that will accept
only two real sampled values for each of a total of four ADC inputs and spit
out a single complex FFT bin (per stream) per FPGA clock.
Can someone point me in the right direction here?
Thanks!
L
> Louis P. Dartez
> Graduate Student
> Center for Advanced Radio Astronomy
> University of Texas @ Brownsville
