Hey Andres,
Closing timing on an FPGA design is not easy. I'd help you but right
now I'm a grad student and drowning in my own work. Sorry! I'll refer
you to this (highly unprofessional) report I gave someone for closing
timing on a ROACH2 design once. That's the best I can offer you now
https://dl.dropboxusercontent.com/u/2832602/roach2_timing.zip
--Ryan Monroe
626.773.0805
On 11/26/2013 09:04 AM, Andres Alvear wrote:
Thanks Ryan,
I have just generated my first .bof after re running the tools for
EDK/ISE/Bitgen successfully but I have not been able to view any speed
optimization so far as you may see in my results in the attached
picture. After the compilation my design ran with a clock rate of
54MHz reaching 216MHz of Bandwidth on each spectrometer. The results
obtained from the constraint generated in the floorplanning process
were introduced in the "system.ucf' file that was located in the
following folders:
/opt/workspace/spectrometer_dctrl_op/XPS_ROACH_base/data
/opt/workspace/spectrometer_dctrl_op/XPS_ROACH_base/implementation
In the "data" folder I removed system.ucf and system.ucf.bac and then
just put my version (with the floorplan) of "system.ucf" in its place.
Then, in the "implementation" folder I replaced the "system.ucf" file
with my version. Finally, I opened the simulink design and then re-ran
it with just EDK/ISE/Bitgen. I had a successful compilation with a new
.bof file. This one is working in the ROACH 1. However, my timing
constrains were not met. I'm going to attach my constrains to see if
you have some idea the possible problems. Given my constrain file
attached, what values would you put in the constrains so that the
system run at 400MHz? What do you think about my Global Timing
Constrains? Specifically what are your thoughts about my timing groups
that were generated from casper_xps toolflow compilation? Are they all
right?
Cheers
Andres Alvear
2013/11/22 Ryan Monroe <[email protected]
<mailto:[email protected]>>
Hey Andres, my strategy has generally been to use plan ahead to
generate a ucf file, which I then place in data/ system.ucf. then
re run the tools for edk ise bitgen.
Works consistently for me
On Nov 22, 2013 11:31 AM, "Andres Alvear"
<[email protected] <mailto:[email protected]>> wrote:
Hi everyone,
I'm working on Speed Optimization with PlanAhead, I've a
Simulink design of a Spectrometer of 2048-channels and 2 ADCs
ADC083000 to 1GSPS in interleaved mode, and I want to meet a
time optimization increasing the bandwidth to 1GHz from the
actual 500MHz and of course increase the numbers of channels
at least to 4096, but with the conventional tool flow is
impossible.
First thing I told the system I wanted it to go to at 250 MHz,
but my actual clock rate is about 120MHz too low!! However the
system is working stable until 125MHz, so I can setup the ADC
clock rate to 500MHz to have 1GSPS getting a 500MHz of
bandwidth to each ADC.
So I have been working on PlanAhead in a Floorplanning
optimization the hardware implemented in the FPGA Virtex-5
SX95T, but after make the floorplanning edit my constraint
file like Ryan Monroe say in his last memo. I got a 23% of
Speed optimization from 120MHz to 148MHz, but I need meet time
at least to 200MHz. However I have problems generating
functional borph executables, and I'm hoping someone can help
me figure out why. Since I'm targeting high speeds. This one
is the error from Borph when I try to run from a ssh session:
root@roach:/boffiles# ./system_2.bof
-bash: ./system_2.bof: Input/output error
Then in a ipython 2.7 terminal to check if you managed to
connect to your ROACH:
In [9]: fpga.is_connected()
Out[9]: True
Let's set the bitstream running using the progdev() command:
In [10]: fpga.progdev('system_2.bof') <-----------generated
from mkbof
Out[10]: 'ok'
See the ROACH and the leds not blinking. I placed these ones
to see the working of my design, but these both not blinking
at all: led0_sync, led1_new_acc.
Do you think that I am in the right the way? Does anyone know
something about these problems?
Cheers!
Andres Alvear
