Here are links to the 2 cores that we use. https://github.com/ska-sa/mlib_devel/tree/master/xps_base/XPS_ROACH2_base/pcores/kat_ten_gb_eth_v1_00_a
https://github.com/ska-sa/mlib_devel/tree/master/xps_base/XPS_ROACH2_base/pcores/ten_gb_eth_v3_00_a Wesley New South African SKA Project +2721 506 7365 www.ska.ac.za On Mon, Feb 10, 2014 at 5:14 PM, Jason Manley <jman...@ska.ac.za> wrote: > We were using Xilinx's free XAUI core for the PHY layer at one time... I'm > not sure if that's still the case though because there was an effort to > write our own at one time. It's been a while since I dug that deep into the > toolflow. > > Jason > > On 10 Feb 2014, at 17:12, Madden, Timothy J. <tmad...@aps.anl.gov> wrote: > > > Implementing a 10GB core is no easy task, considering you must sync. > many serial transceivers together. Cool. Good job. > > > > Tim > > > > ________________________________________ > > From: Jason Manley [jman...@ska.ac.za] > > Sent: Monday, February 10, 2014 9:09 AM > > To: Madden, Timothy J. > > Cc: Casper Lists > > Subject: Re: [casper] 10GB Ethernet > > > > We have implemented our own 10GbE core. It's free open-source! > > > > Jason > > > > On 10 Feb 2014, at 16:50, Madden, Timothy J. <tmad...@aps.anl.gov> > wrote: > > > >> Folks > >> > >> How does the 10GB Ethernet work on the Roach boards? In most Xilinx > applications, the 10GB ethernet is generated by Xilinx IP blocks that have > an expensive license, on the order of $22k. > >> > >> I have heard nothing about licensing fees for the 10GB Roach yellow > block. Any ideas on this? > >> > >> Tim Madden > >> Argonne Lab > >> > > > > >
