Hi Katty,
That's just the regular multiplex ("Mux") block -- not the time division
multiplexing one, which is literally called "Time Division Multiplexer" :-)
The block you've got does
if sel==0:
dout = d0
else if sel==1:
dout = d1
I.e, it won't interleave streams, it just lets you pick between the two.
This won't do the time multiplexing you want. I'm pretty sure you want to
reconfigure the FFT and PFB by changing the "number of simultaneous inputs"
parameter from 2^2 to 2^3, then connect the 8 ADC outputs straight to the
PFB.
Cheers,
Jack
On 13 February 2014 11:44, katherine viviana cortes urbina <
[email protected]> wrote:
> Hi Jack,
>
> Thanks for your comments. I modified the design to including the time
> division multiplexing block. But I have a question, this block have
> differents inputs parameters, e.g "sel" I connected a slice but I dont
> that clock would connect this. I think to connect a sync0 (clock of ADC) or
> other clock, any idea?
>
> Cheers Katty
>
> pd: to see the attachments
>
>
> 2014-02-11 18:17 GMT-03:00 Jack Hickish <[email protected]>:
>
> Hi Katty,
>>
>> I think the root of your problems might be that you are using simulink's
>> multiplexer blocks on your ADC outputs rather than Xilinx's. Then you end
>> up with multidimensional signals, which the Xilinx blocks don't like. The
>> Xilinx time division multiplexing block is in the Xilinx "Basic Elements"
>> blockset. I think this is supposed to do what you want, but I doubt it will
>> work with the toolflow without changes.
>>
>> In any case, to multiplex as you're trying to do would require an FPGA
>> clock of 500MHz (eek!) to process the streams. If I understand your email
>> correctly, you'd be better off processing 8 streams at 250MSps using an
>> FIR/FFT implementation with 8 parallel inputs. This should just be a simple
>> parameter change on the pfb-fir and fft blocks.
>>
>> Cheers,
>> Jack
>>
>>
>> On 11 February 2014 20:54, katherine viviana cortes urbina <
>> [email protected]> wrote:
>>
>>> Hi all,
>>>
>>> I would like to know how to use the mux block in the design single
>>> spectrometer of 2 GSps at 1 GHz bandwidth (with interleaved sampling
>>> "ADC2X1000-8bit"), e.g the idea that is in the design attachments.
>>> In this design after the mux each stream is 500 MSps (500x4 stream), but
>>> I have the following error:
>>>
>>> Error in port widths or dimensions. Invalid dimension has been
>>> specified for output port 1 of 'a1/pfb_fir_real1/pol1_in1_coeffs/din'.
>>>
>>> Error in port widths or dimensions. Input port 1 of '
>>> a1/pfb_fir_real1/pol1_in1_coeffs/Delay1' is a one dimensional vector
>>> with 1 elements.
>>>
>>>
>>> any idea?
>>> is the problem delay?
>>>
>>> Cheers
>>>
>>> Katty
>>>
>>
>>
>
