Hi Norbert
It's been a while since I worked on transceivers, so I may be wrong when
I say this, but I think that you need to generate a separate core for
each transceiver on the FPGA. You can't modify a core, after you have
generated it, to make it work for another transceiver.
My suggestion would be to generate cores for all possible transceivers
on the chip, and then if you only want to use one of the transceivers in
your final design, the best solution would be to use a script that
decides, at compile time, which core to include into the design.
Regards,
Simon
On 03/03/2014 02:42 AM, Norbert Bonnici wrote:
Hi Casperites,
I recently built an Aurora yellow block for ROACH 2 and now I'm in the
process of generalising it. As you may know when you create a coregen
for a high speed transceiver you are asked to choose where the
transceiver quad tiles are going to be and which clock you need to use.
What I'm not sure coregen is doing, is how these configurations are
propagated throughout the system. Anyone knows how I can choose which
tile and clock to use manually so I can have generic to switch between
each XAUI port?
Thanks in advance!
Best regards,
Norbert
