Hi Joe,
If you've already followed the careful start up recipe let us know
so we can think about what you are seeing. Otherwise...
The Hittite ADCs need to be programmed after clock and power
are applied otherwise they can deliver all sorts of nonsense.
And then the FPGA needs to be "trained" as to when to capture
the high speed serial bit streams from the ADC ICs. Then,
valid data will be available to the fabric of the FPGA.
The user guide I somewhat recently added to
https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#ADC16x250-8_coax_rev_2_Gateware_.28aka_yellow_block.29_and_Software
explains the process more clearly (I hope).
Matt
On Tue, 25 Mar 2014, Kujawski, Joseph wrote:
Date: Tue, 25 Mar 2014 09:33:17 -0400
From: "Kujawski, Joseph" <[email protected]>
To: casper list <[email protected]>
Subject: [casper] ADC16-8 conversion problem
I have a simple design which pipes the input of one of the ADC16 channels to
the 1GbE block to be
recorded on an external computer. The clock input for the ROACH board is set
to 200MHz and there
is a 20MHz, 20mVp-p, AC coupled input to channel A1 of the ADC (verified on an
oscilloscope).
Reading the values sent across the 1GbE, I get the following:
255
255
255
255
255
0
0
0
0
0
255
255
255
255
255
0
0
0
0
0
Which looks like the ADC is saturating, however, the CASPER documentation
indicates that the full
scale input of the ADC is 2V p-p.
For reference, I have successfully transferred counter data through the
ethernet port, so I know
that this interface is capable of transferring values besides x00 and xFF.
Does anyone have suggestions as to how to fix this problem?
-Joe Kujawski
