Hi Ramesh, When the data gets to your simulink design it will be multiplexed with 4 adc channels per adc yellow block output, so you'll have to demux yourself or deal with the mulitplexing in your code somehow. I don't think there's a casper block to demultiplex this for you, though there is a serial-to-parallel block in the Xilinx library which probably does what you want. The sample and hold block in the setup you describe should work too (with a sample rate of 4 cycles). You would want to wire the sync input to the chan_sync output of the adc block, taking care to properly account for the timing of the chan_sync relative to the data (I can't remember if it precedes adc channel 0 by a clock cycle, or comes at the same time -- the documentation should tell you).
As you suggest, you can combine 4 12 bit outputs with the bus_convert block to be clocked into the 10GbE block -- just cast from Fix12_11 to Fix16_15 format. Cheers, Jack PS. don't forget to run the adc calibration script linked on the wiki before trying to use the adc data! On 24 June 2014 09:27, Ramesh Karuppusamy <[email protected]> wrote: > > Hello All, > > I am seeking some guidance on a simple total power detector system that I am > putting together. > > I would like to sample 8 to 16 signals at a low rate of 10 KHz with the > ROACH1 and transmit the data on the 10GbE. Someone did suggest a simple > USB-based ADC, but we like the ROACH based set up, as it involves little work > on the receiving side. Therefore, I purchased 64-input 12-bit ADC board. The > plan is to clock the ADC at 20 MHz and downsample to 10 KHz inside the FPGA. > > I read the yellow block documentation at > https://casper.berkeley.edu/wiki/X64_adc, which says the FPGA will be clocked > 4x the ADC rate and that the outputs are multiplexed on the dout<n> pins. Is > there a casper block to de-multiplex the data on these pins? Alternatively, > can this be a bank of 4 “sample_and_hold” (found inside Casper DSP block set) > with 4-cycle delay, with the inputs delayed by zero, one, two and three > cycles? > > Now can the four 12-bit outputs above combined using a bus_convert to a > 64-bit input that can be clocked in to the 10GbE block? > > Thanks for your time! > > Cheers, > Ramesh > >
