Hi Oliver, It is a bit tough to tell where your signals are coming from with the picture you have included. I see a few issues though. When connecting Xilinx blocks to Simulink/Matlab blocks, you need to go through a special block. Connecting your delay blocks directly to a scope will cause errors, and you should insert a "Gateway Out" block on each of those 3 wires. This would be opposite to the main error you described, namely that the scope *cannot *be driven by Xilinx blocks.
Casper has taken care to develop some of these yellow blocks that will take Xilinx inputs directly, for example the "software register" block. Unfortunately I don't have a copy of tut3.mdl right now (I'm remote at the moment) but I would assume this quant0 block needs xilinx/casper blocks attached to it on the left. If your "quant_gain" From flag is coming from a Simulink constant, then this error will occur. If you replace it with a Xilinx constant (and be sure and check the box "Sampled Constant") then it should be ok. --Laura On Tue, Oct 21, 2014 at 9:50 AM, Wang Jinqing <[email protected]> wrote: > Hi, > I have download the tut3.mdl. And I found than for the inports,such as > [quant_gain], the sysgen always give out such error "The input ports on > this block must be driven by other Xilinx blocks" during simulation,see the > appendix. So then I have change a xilinx constant block,it seem good. But > the [quant_gain] is an inport, that is an interface to the software, so > which xilinx is suitable? > > Best Regards. > Oliver Wang > > > >
