Hi All, I'm a little confused about addressing in the DRAM controller on a ROACH. If, for example, I set the address to be 0 and toggle the cmd_valid on the off (2 clk cycles). I receive (at some arbitary time later) 2 144 "words" (of which only 128 bits are data).
If I now fill up a section of the dram with a series of numbers from python: x = arange(1000, dtype="int32") write_dram(x.tostring(), 0 , True) I set the dram address to be 0 in the controller and readout the first "128" bits I get [0,1,2,3], then I readout the second "128" bits (clk cycle 2) and I get [4,5,6,7]. If I then set the address to 1 the process continues. Next "144" bits are [8,9,10,11], the next clk cycle [12,13,14,15]. This to me makes me think that each register is 256(288) bits wide. The cpu interface on the other hand claims that the register is only 128(144) bits wide. e.g. here is what I would expect from the docs given the above dram values address | fpga | cpu 0 | [0,1,2,3] [4,5,6,7] | [0,1,2,3] 1 | [8,9,10,11] [12,13,14,15] | [4,5,6,7] I'm sure I'm missing something obvious here.... Ross -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
