Hi, Peter, On Jan 12, 2015, at 1:11 AM, Peter Niu wrote:
> In our model, We need ADC clock frequency up to 250Mhz. Our ADC boards are > ADC16*250-8.We are using adc16*250-8 yellow block in our model modified based > PAPER model .However when I changed the XSG core config/User IP Clock > Rate(MHz) to 250 Mhz and System Generator/FPGA Clock Period(ns) to 4ns, it > could not create bof file,something like the following: > > ERROR:LIT:667 - Block 'MMCM_ADV symbol [...] has its target frequency, FVCO, > out of range. I'm surprised that you did not get a DRC (design rule check) error earlier in the build process. The ADC chips on the ADC16 board can sample as high as 250 Msps when the ADC16 is running in 16 input mode, but MMCM limitations prevent using some sample rate ranges. In short, the ADC16 board is limited to a maximum of 240 Msps in 16 input mode. For details, see this new section of the CASPER wiki: https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations > Now, The system work in 250Mhz clock rate while the model bof file is > crearted in 200Mhz. It looks no problem in sending the correct data packets, > but I am not sure whether it run normally.In theory , the input data rate is > 250Mhz*8bits*32=64Gbits/s,after fft, EQ ,the data rate becomes 32Gbits/s,we > have 4 10Gbe ports to send out data.Each ports will have32/4=8Gbits/s,(if we > use 200MHz,this data rate is about 6.4Gbits/s )I don't know whether it is ok > for the transition capability of the 10Gbe NICs(10Gbits/s). > Could anyone help me please? It may seem like it works at 250 MHz, but you are asking for problems if you clock the FPGA faster than the design was built for. You could rebuild the design for 240 Msps and it should work OK (assuming the build can meet timing at 240 MHz). Hope this helps, Dave
