[pardon the triple-post, if that happened; I appear to have mailing list issues]
Hey all, I'm designing a FX correlator on ROACH2 boards, which is targeting a user clock rate of 312.5 MHz. However, I see TONS of failures similar to the one posted below (see image) It appears that there is a super-high fanout bus which connects all the registers and shared-memories on the processor side. I tried mitigating this by minimizing the number of yellow blocks, but this only made the problem worse. We might be able to add a cycle of latency to this bus, resolving the timing error and making my day. Anyone have the experience to know how to do this? Or another way to resolve the issue? I'm all out of ideas on my end Thanks in advance! Image: https://dl.dropboxusercontent.com/u/2832602/epb_timing_fail.png --Ryan
