Hi Tim, If you don't mind sharing your design, I'll put it up on the Casper wiki, where i think it would be useful for others trying to use the dram.
Cheers, Jack On Thu, 16 Apr 2015 7:19 am Madden, Timothy J. <[email protected]> wrote: > Folks > > After reverse engineering the dram on ROACH2 here is what one should know. > > 1. The dram on roach2 is different from roach1. > On roach1, the user can read and write 144 size words to the dram with > the buss set not to 288 bits. > On roach2, the data buss is always 288 bits, regardless of the "use wide > buss" setting. > 2. Of one wants to stream dram data to a DAC on a roach 1, for MKID > applications we do this: > Read every other clock cycle by toggling cmd ack on each clock. > 144 bit words will steam out every clock that can drive the DAC. > > On roach2, we read 288 bit words every other clock cycle by toggling > cmd ack on every clock. > Then we use a mux to convert the 288 bit words down to a series of > 144 bit words on every clock. > > The dram should be set to 200MHz, not 240MHz or something else. The CORE > generator has all its constraints > set up for 200MHz. Note that this 200MHz has nothing to do with your > fabric clock, as it comes > from a different PLL on the FPGA. The yellow block does not interface to > the dram itself, but simply FIFOs. > When you write to the dram yellow block, you write to FIFOs that cross the > clock domains. For streaming > 144 bit data to DACs, you are reading 288 bit data from the dram at 1/2 > your fabric clock rate. This gives > lots of time for the FIFOs to read from the dram in little 8 word bursts > and still deal with the dram refresh. > > I post this because we got confused by the documentation on the casper > website. Also, we are moving from > ROACH to ROACH2, and did not know the little differences in the dram. > Also, it is natural to assume that the > yellow block talks directly to the xilinx ddr3 controller and the ports > correspond to the UI interface > documented in the xilinx memory generator docs. This is not the case. The > yellow block reads and writes > fifos, and the ddr stuff is all hidden. > > The dram is a nice design by the way. I am just pointing out some details > to save other folks some time. > > Tim Madden > Argonne Lab > >
