Simon, I think you'll find that the timing error has been ignored in the past.
John > I have a timing error when I try and compile firmware containing the > dac_mkid and adc_mkid yellow blocks and a LUT. I stripped out most of the > code in the original bof file to just leave those blocks and still got the > same errors). When compiling on a 64 bit linux system for a roach 1/sx95t > I get the following error message: > >>PAR could not meet all timing constraints. A bitstream will not be > generated. >> >>To disable the PAR timing check: >> >>1> Disable the "Treat timing closure failure as error" option from the > Project Options dialog in XPS. > > Further back in the mat lab output is: > ---------------------------------------------------------------------------------------------------------- > Constraint | Check | Worst Case | > Best Case | Timing | Timing > | | Slack | > Achievable | Errors | Score > ---------------------------------------------------------------------------------------------------------- > * PERIOD analysis for net "mba15_srd1_adc_m | SETUP | > 1.526ns| 2.380ns| 0| 0 > kid/mba15_srd1_adc_mkid/dcm_clk" derived | HOLD | > -0.104ns| | 10160| 239632 > from NET "mba15_srd1_adc_mkid/mba15_srd1 | MINPERIOD | > -0.093ns| 3.999ns| 1| 93 > _adc_mkid/drdy_clk" PERIOD = 3.9062 ns HI | | > | | | > GH 50% duty cycle corrected to 3.906 nS | | > | | | > HIGH 1.953 nS | | > | | | > ---------------------------------------------------------------------------------------------------------- > * TS_mba15_srd1_adc_mkid_mba15_srd1_adc_mki | MINPERIOD | > -0.093ns| 3.999ns| 1| 93 > d_dcm_clk_0 = PERIOD TIMEGRP "mba15_srd1_ | | > | | | > adc_mkid_mba15_srd1_adc_mkid_dcm_clk_0" T | | > | | | > S_adcmkid1_DRDY_I_n HIGH 50% | | > | | | > ---------------------------------------------------------------------------------------------------------- > * TS_mba15_srd1_adc_mkid_mba15_srd1_adc_mki | MINPERIOD | > -0.093ns| 3.999ns| 1| 93 > d_dcm_clk = PERIOD TIMEGRP "mba15_srd1_ad | | > | | | > c_mkid_mba15_srd1_adc_mkid_dcm_clk" TS_ad | | > | | | > cmkid1_DRDY_I_p HIGH 50% | | > | | | > ---------------------------------------------------------------------------------------------------------- > > As far as I know this firmware has been compiled before - on the other > hand > it is possible that the timing error has just been ignored however that > does not seem the safest of options. Has anyone else seen this problem? > I've looked at adding delays in all sorts of places but so far no luck. >
