Hi Dave,
Thanks for having a look. I'm pretty sure the clocks are correct. The
high speed clock is 750/4 = 187.5 MHz and the low speed clock is 750/12
= 62.5 MHz, a factor of 3 different. (I'm purposefully using low clock
rates with the goal of increasing the rates until it dies.) The SDR
case, that works, has the high speed clock at 750/2 = 375 MHz and the
low speed clock is unchanged. As a sanity check, the serial waveform,
as viewed on an oscilloscope, is identical in both cases for any given
bit pattern.
Rich
On 5/19/2015 5:45 AM, [email protected] wrote:
Message: 1
Date: Mon, 18 May 2015 14:14:41 -0700
From: David MacMahon<[email protected]>
Subject: Re: [casper] Select IO DDR Puzzle
To: Rich Lacasse<[email protected]>
Cc: casper list<[email protected]>
Message-ID:<[email protected]>
Content-Type: text/plain; charset=us-ascii
Hi, Rich,
What are the frequencies of the various clocks? I think you want the OSERDES
CLKDIV to be the same freq as the parallel data's clock. For 6 bit parallel
data, you want the freq of the OSERDES CLK to be 6*freq(CLKDIV) in SDR mode and
3*freq(CLKDIV) in DDR mode. I think the same is true for the ISERDES. I'm not
sure I'm discerning things correctly from the VHDL, but it looks like maybe you
are running CLKDIV at 87.5 MHz instead of 125 MHz?
Dave
