Hi Homin, Both Jack and myself have worked on this and Jack seems to have found a fix to get the QDRs working at any frequency!
Read this thread for more details about the issues we had https://www.mail-archive.com/casper@lists.berkeley.edu/msg05924.html This is an issue from when the board was designed and has caused us endless trouble with the QDR controller. I constrained the first registers on the FGPA to be the closest register to the physical pin so that we wouldnt have the added problem with routing delays in the FPGA. This can be seen in the system.ucf in the ska-sa/mlib_devel repository. Regards Wesley Wesley New South African SKA Project +2721 506 7300 www.ska.ac.za On Thu, May 28, 2015 at 3:13 AM, Homin Jiang <ho...@asiaa.sinica.edu.tw> wrote: > Dear All: > > Recently i found out the locations I/O pins for qdr2/ROACH2 are not in the > same FPGA area.(from the Planahead/device map). Some of them are in the > left edge of the device, and some of them are in the middle of the device. > Is there someone experienced this problem and have constraints in hand to > share with ? > > regards > homin jiang > >
