Dear Kaustubh,
" iadc which I am clocking at 560 MHz (hence the board runs at 140 MHz).
The data comes in to a 10 GBe block. After 800 clock cycles, "
The data rate goes like this as per your input ..
5.7142 us is the time for 800 clock cycles @ 140 MHz.
So the data rate calculation goes by the 8/10 coding technique .
where assuming 42 bytes is the UDP header size.
(((1000000/5.71428) *(800*8) ) + 42 )*10 bits = ~11.20 Gbit.
You were exceeding the through put limitations.
ref: https://casper.berkeley.edu/wiki/Tutorial_10GbE
Experts please advice if it is wrong.
Cheers
Indrajit.
On Tuesday 04 August 2015 06:37 PM, Kaustubh Rajwade wrote:
Hi Indrajit,
So I am using the iadc which I am clocking at 560 MHz (hence the board
runs at 140 MHz). The data comes in to a 10 GBe block. After 800 clock
cycles, I send an eof to the block. Thats pretty much it. The idea is to
just free stream the data continuously without any break. For a packet
length of 800 or less, this works fine. For a longer packet length the
core locks up.
Kaustubh
On Tue, Aug 4, 2015 at 7:33 AM, indrajit <[email protected]
<mailto:[email protected]>> wrote:
Dear Kaustubh,
Can you describe your system block diagram,
What ADC, what exactly you want to do ..
--Indrajit
On Tuesday 04 August 2015 12:57 PM, Kaustubh Rajwade wrote:
Yes, but I think that in their case they are running the board at 200
MHz which is greater than 156 MHz. In this case, it is less than 156 so
the design should work fine. Am I missing something? Does it have
something to do with the 8/10 encoding such that the effective clock
rate of the 10 Gbe is less than 156 MHz?
Let me know.
Thanks,
Kaustubh
On Tue, Aug 4, 2015 at 12:13 AM, indrajit <[email protected]
<mailto:[email protected]>> wrote:
Dear Kaustubh,
please go through this page
https://casper.berkeley.edu/wiki/Tutorial_10GbE
search for "Add a counter to limit the data rate "
In that they mentioned about the limitations.
1) You want to stream the data continuously at 140 MHz using 10GBe. ?
Hi All,
I have a simple design on Roach 1 where I stream packets over the 10Gbe
network. Currently, I am running the board at 140 MHz. When I try to send
packets of length >800, the core locks up. I believe that the 10 Gbe core
is synchronized with 156 MHz crystal on the board so this design should
work fine on a lower clock rate.
Can someone shed some light on this?
Thanks,
Cheers,
Kaustubh
On Tuesday 04 August 2015 12:41 AM, [email protected] wrote:
10Gbe transmission on roach 1 (
--
Thanks and regards
______________________
Indrajit Vittal Barve
Engineer,
Radio Astronomy Group,
Indian Institute of Astrophysics,
Gauribidanur.
Pin : 561208
Mobile : +91-9845432754.
Office : +91-8155291655.
