Hello CASPER,
I am implementing one spectrometer with one Shared BRAM yellow block with
the next specifications:
1. ROACH 1
2. ADC083000: ADC0 (ZDOK0). 8 outputs per clock.
3. Bw: 500 MHz
4. N° of channels: 2048
5. One Shared BRAM with:
- Address width: 11
- Data width: 32 bits.
I've decided implement a mux with delays to pass 4 parallel streams to
serial. Finally the idea is map into memory in a correlative order from 0
to 2047.
I have attached snapshot of my simulink model and results.
https://drive.google.com/file/d/0B9LbvB1SpcjONm5WR0ZZVmRHLUU/view?usp=sharing
https://drive.google.com/file/d/0B9LbvB1SpcjOWmZ0cVdGdmRaYUE/view?usp=sharing
https://drive.google.com/file/d/0B9LbvB1SpcjONlNwVnh5Qi01clE/view?usp=sharing
As you see in the picture I am packing the 4 parallel streams in one bram
in order to unpack 2048 channels at once instead 512 per bram (I mean a
design with 4 Shared BRAM).
Does anyone know whether simulations involving the Shared BRAM yellow block
are supposed to work? I'd like to simulate the address into the memory. I
am not pretty sure about the write and read timing for Shared BRAM.
Does anyone know whether theese z^-511 delays are good enough for this kind
of implementation? I'm doing something wrong?
Cheers,
Andrés Alvear
Universidad de Chile
