Hi everyone, I'm having quite a lot of problems getting a particular design to compile, XPS consistently reporting timing errors. The design is a wideband spectrometer, somewhat similar to the tutorial 3 design. I'm running an iADC at 1024 MHz, and the FPGA at 256 MHz. It is a two-polarisation design, with a 64k-point PFB and FFT (for 32k channels) in each polarisation. I am running the PFB and FFT blocks in "two-polarisation" mode, so there are just one of each block. I am using the Vacc block from the xBlocks repository.
I should add at this point that the same design with 16k channels compiles successfully at this speed, and that the 32k channel design compiles at slower speeds (e.g. 200 MHz FPGA). The timing reports suggest negative slack in the PFB and Vacc blocks. I've tried adding various combinations of latency in each, however no permutations have resulted in substantial improvements. The overwhelming majority of the errors are reported by the Vacc block. I have also tried replacing the xBlocks Vacc block with the wide_bram_vacc block in 64-bit mode, however this results in even more timing errors (and without the option to adjust latencies). I've tried various combinations of latencies suggested previously on the mail archive, but again nothing has really given any improvement. Am I simply pushing such a large design too hard? Is the only option to slow it down or is there some strategic method I can adopt to get closer to timing closure? Suggestions much appreciated! Thanks Michael
