Hi jack, thanks for your help.
Greetings, Roberto El vie., 23 oct. 2015 a las 19:13, Jack Hickish (<jackhick...@gmail.com>) escribió: > Hi Roberto, > > I added an MSSGE block (roach2, clocking off adc0 at 2000/32 MHz) and a > software register on one of the adc outputs to your adc5g_dmux_x2 model > and compiled using our setup at UC Berkeley (Xilinx 14.7). > > I got a segfault! > > In your adc yellow block mpd file I changed the lines: > #ADC0 > PORT adc0_ctrl_clk_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc0_ctrl_clk90_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc0_ctrl_clk180_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc0_ctrl_clk270_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > > #ADC1 > PORT adc1_ctrl_clk_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc1_ctrl_clk90_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc1_ctrl_clk180_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > PORT adc1_ctrl_clk270_out = "", DIR = O, SIGIS = CLK, CLK_INPORT = > adc_clk_p_i, CLK_FACTOR = "1.0 / 2 " > > to: > > #ADC0 > PORT adc0_ctrl_clk_out = "", DIR = O, SIGIS = CLK > PORT adc0_ctrl_clk90_out = "", DIR = O, SIGIS = CLK > PORT adc0_ctrl_clk180_out = "", DIR = O, SIGIS = CLK > PORT adc0_ctrl_clk270_out = "", DIR = O, SIGIS = CLK > > #ADC1 > PORT adc1_ctrl_clk_out = "", DIR = O, SIGIS = CLK > PORT adc1_ctrl_clk90_out = "", DIR = O, SIGIS = CLK > PORT adc1_ctrl_clk180_out = "", DIR = O, SIGIS = CLK > PORT adc1_ctrl_clk270_out = "", DIR = O, SIGIS = CLK > > The segfault goes away (and the build fails with an HDL syntax error). To > be honest I don't remember (or perhaps I never knew) how the CLK_INPORT > and CLK_FACTOR attributes work, but perhaps this information will help set > you in the right direction. > > Cheers, > Jack > > On Fri, 23 Oct 2015 at 18:01 Roberto F. <rmfuent...@ing.uchile.cl> wrote: > >> Hi Jack, >> >> I'm using Xilinx 14.5, and i can compile the original yellow block. >> >> I don't have a branch in the casper repository, but i upload the library >> to a git repository of my own. Here is the link >> https://github.com/amermelao/mlib_devel_roberto.git. My model is caled >> adc5g_dmux_x2. >> >> Cheers, Roberto >> >> El mar., 20 oct. 2015 a las 13:29, Jack Hickish (<jackhick...@gmail.com>) >> escribió: >> >>> Hi Roberto, >>> >>> That's an interesting one. I don't think I've ever seen xps segfault. >>> >>> First, are you using the latest (14.7) versions of the Xilinx tools? >>> Second, can you compile the original yellow block OK? >>> >>> Other than go through the changes you've made step by step until you >>> identify the what's broken, I'm not really sure what to suggest. If your >>> code is checked into a branch of mlib_devel somewhere I'd be happy to try >>> and run it on my setup here if you think that'd help. >>> >>> Cheers, >>> Jack >>> >>> >>> >>> >>> On Mon, 19 Oct 2015 at 19:58 Roberto F. <rmfuent...@ing.uchile.cl> >>> wrote: >>> >>>> i'm trying to do a yellow block similar to the 83000x2. Instead of >>>> using the 83000 adc i want to do it with the adc5g adc (for roach2). >>>> >>>> I've used the tutorial 7 of casper for reference and some other >>>> documents to build the yellow block (i also looked how the adc5g was done). >>>> >>>> I'm stuck becuase when the toolflow runs xps -nw -scr run_xps.tcl >>>> system.xmp i get a Segmentation fault. I tried to open xps manualy and the >>>> load system.xmp but it closes. Could someone guide towards the origin of >>>> the bug? It's on the VHDl code or in the port definition or something. >>>> >>>> Atte. >>>> >>>> Roberto Fuentes P. >>>> _________________ >>>> >>>> >>>> Roberto M. Fuentes P. >>>> >>>
