Hi Adrian,
There’s an open-source TtD converter design available at OHWR that might be of interest to you. The paper describing it is http://arxiv.org/pdf/1303.6840v1.pdf and the repository is at http://www.ohwr.org/projects/tdc-core/repository. Cheers, Peter From: [email protected] [mailto:[email protected]] On Behalf Of Dan Werthimer Sent: Saturday, December 26, 2015 1:00 PM To: Adrian Sinclair <[email protected]> Cc: CASPER Mailing List <[email protected]> Subject: Re: [casper] Asynchronous inputs? hi adrian, yes, an fpga inputs can be used as an asynchronous input: an fpga input block has several D flip flops, but they are optional. several people have implemented time to digital converters with FPGA's. and there a bunch of papers on this. you can try googling "time to digital converter FPGA". these guys get 30 ps resolution ! : http://cds.cern.ch/record/1158663/files/p383.pdf i think casperite rick raffanti has done something like this, so i'm ccing rick on this. if you only need 0.5 ns resolution, a simple technique is to use the fpga's clock generators to generate several clock phases: eg: 0, 45, 90, 135, 180, 225, 270 degrees, and then send the input to D flip flips clocked at these different phases.... if you clock at 250 MHz, then you would get 0.5 ns resolution. if you only need 1 ns resolution, you can use the input block's flip flop and shift registers - i think the input block is already set up to do QDR - quad data rate sampling. best wishes, dan On Sat, Dec 26, 2015 at 12:27 PM, Adrian Sinclair <[email protected] <mailto:[email protected]> > wrote: Hello, I'm wondering if anyone knows of a way to input an asynchronous signal to the Virtex 6 on the ROACH2. My goal is to design an all internal time-to-digital converter with sub-clock period resolution, and would like the ability to send a signal through a string of buffers with registers tapped after each one, and upon the arrival of the clock pulse sample the entire buffer lines registers. More specifically my question is, Does the signal get latched when using gpio's, even when not packing a register in the pad? Thanks in advance, Adrian Sinclair
