Hi Jack Thanks for the explanation.
Regards RP 2016-02-20 21:56 GMT-06:00 Jack Hickish <[email protected]>: > Hi Rolando, > > This is wrong -- the User IP clock source should be adc0_clk, at 24 MHz. > If you see a design with an ADC, but the clock source is set to to > sys_clk, this is *almost always* a mistake. > > Jack > > On Sat, 20 Feb 2016 at 19:04 Rolando Paz <[email protected]> wrote: > >> Hi >> >> I have a question about the "User IP clock source" value on the model >> file Leuschner Spectrometer, because this value is programmed as "sys_clk" >> and the ADC has a value "ADC clock rate" of 96MHz. >> >> As I see in Leuschner circuit an external clock is used, then why appears >> sys_clk? >> >> https://casper.berkeley.edu/wiki/Leuschner_Spectrometer >> >> Regards >> >> Rolando Paz >> >> >>
