[casper] yellow block for 2Gsps adc/dac

[Matt Strader]

Hello Casperites,

I am working on a roach2 yellow block for a new 12bit,  2.0 Gsps ADC/DAC
board designed at Fermilab.  I am having trouble with clocks.  The ADC/DAC
board is providing me with a 500 MHz clock over a particular zdok pair.  My
yellow block takes this into an mmcm and divides it down to 250 MHz to be
used as the fabric clock.

When testing it, I set the adc/dac clock running, then program the roach2.
When I call KatcpFpga.estimate_fpga_clock() it returns 167 MHz instead of
the expected 250 MHz.

I have attached what I think are the relevant snippets from my yellow
block.  The rest of it can be found at
https://github.com/mstrader/mlib_devel
Any ideas what could be the problem?

Thanks,
Matt Strader

#########################
/home/kids/mlib_strader/xps_library/@xps_adcdac_2g/xps_adcdac_2g.m
#########################
% external ports
ucf_constraints_clock  = struct('IOSTANDARD', 'LVDS_25', 'DIFF_TERM', 'TRUE', 
'PERIOD', '2 ns');
ucf_constraints_term    = struct('IOSTANDARD', 'LVDS_25', 'DIFF_TERM', 'TRUE');
ucf_constraints_noterm = struct('IOSTANDARD', 'LVDS_25');
mhs_constraints = struct('SIGIS','CLK', 'CLK_FREQ','500000000');
adcport1 = [s.hw_sys, '.', 'zdok1'];
ext_ports.data0_smpl_clk_p = {1  'in' ['adc_data0_smpl_clk_p'] 
['{',adcport1,'_p{[20],:}}'] 'vector=false'  mhs_constraints ucf_con
straints_clock};
ext_ports.data0_smpl_clk_n = {1  'in' ['adc_data0_smpl_clk_n'] 
['{',adcport1,'_n{[20],:}}'] 'vector=false'  mhs_constraints 
ucf_constraints_clock};

if  strfind(s.clk_sys,'adc')
  misc_ports.adc_clk_out    = {1 'out' [s.adc_str,'_clk']};
  misc_ports.adc_clk90_out    = {1 'out' [s.adc_str,'_clk90']};
  misc_ports.adc_clk180_out    = {1 'out' [s.adc_str,'_clk180']};
  misc_ports.adc_clk270_out    = {1 'out' [s.adc_str,'_clk270']};
end

# zdok1_clk0_p[1] # data0_clk_p
# zdok1_clk0_n[1] # data0_clk_n

#########################
/home/kids/mlib_strader/xps_base/XPS_ROACH2_base/pcores/adcdac_2g_interface_v1_00_a/hdl/verilog/adcdac_2g_interface.v
#########################

    wire data0_smpl_clk;
    IBUFGDS #(.IOSTANDARD("LVDS_25"))
        IBUFDS_inst_adc_clk(
          .O(data0_smpl_clk),
          .I(data0_smpl_clk_p),
          .IB(data0_smpl_clk_n)
          );


    //  -- MMCM INPUT


    wire mmcm_clk_in;
    BUFG BUFG_data_clk(
        .I(data0_smpl_clk),
        .O(mmcm_clk_in));



    //  -- MMCM

    wire smpl_clkdiv;
    wire mmcm_smpl_clkdiv_out;
    wire mmcm_smpl_clk_out;
    wire mmcm_clk_out_0;
    wire mmcm_clk_out_90;
    wire mmcm_clk_out_180;
    wire mmcm_clk_out_270;
    MMCM_BASE #(
       .BANDWIDTH("OPTIMIZED"),   // Jitter programming 
("HIGH","LOW","OPTIMIZED")
       .CLKFBOUT_MULT_F(12.0),     // Multiply value for all CLKOUT (5.0-64.0).
       .CLKFBOUT_PHASE(0.0),      // Phase offset in degrees of CLKFB 
(0.00-360.00).
       //Input 500 MHz -> 2 ns
       .CLKIN1_PERIOD(2.000),       // Input clock period in ns to ps 
resolution (i.e. 33.333 is 30 MHz).
       .CLKOUT4_CASCADE("FALSE"), // Cascase CLKOUT4 counter with CLKOUT6 
(TRUE/FALSE)
       .CLOCK_HOLD("FALSE"),      // Hold VCO Frequency (TRUE/FALSE)
       .DIVCLK_DIVIDE(6),         // Master division value (1-80)
       .REF_JITTER1(0.0),         // Reference input jitter in UI (0.000-0.999).
       .STARTUP_WAIT("FALSE"),     // Not supported. Must be set to FALSE.

       //Output 250 MHz 0deg for fpga
       .CLKOUT2_DIVIDE(4),
       .CLKOUT2_DUTY_CYCLE(0.5),
       .CLKOUT2_PHASE(0.0),

       //Output 250 MHz 90deg for fpga
       .CLKOUT3_DIVIDE(4),
       .CLKOUT3_DUTY_CYCLE(0.5),
       .CLKOUT3_PHASE(90.0),

       //Output 250 MHz 180deg for fpga
       .CLKOUT4_DIVIDE(4),
       .CLKOUT4_DUTY_CYCLE(0.5),
       .CLKOUT4_PHASE(180.0),

       //Output 250 MHz 270deg for fpga
       .CLKOUT5_DIVIDE(4),
       .CLKOUT5_DUTY_CYCLE(0.5),
       .CLKOUT5_PHASE(270.0),
    )
    CLK_MMCM (
       // Clock Outputs: 1-bit (each) output: User configurable clock outputs
       .CLKOUT0(mmcm_smpl_clkdiv_out),
       .CLKOUT0B(),
       .CLKOUT1(mmcm_smpl_clk_out),
       .CLKOUT1B(),
       .CLKOUT2(mmcm_clk_out_0),
       .CLKOUT2B(),
       .CLKOUT3(mmcm_clk_out_90),
       .CLKOUT3B(),
       .CLKOUT4(mmcm_clk_out_180),
       .CLKOUT5(mmcm_clk_out_270),
       .CLKOUT6(),
       // Feedback Clocks
       .CLKFBOUTB(),
       // Status Port
       .LOCKED(adc_mmcm_locked),
       // Clock Input
       .CLKIN1(mmcm_clk_in),
       // Control Ports
       .PWRDWN(1'b0),       // 1-bit input: Power-down input
       .RST(1'b0),             // 1-bit input: Reset input
       // Feedback Clocks
       .CLKFBIN(smpl_clkdiv)      // 1-bit input: Feedback clock input
    );

    //  Now put all mmcm outputs through a BUFG

    //250 MHz clocks with phases 0,90,180,270 for the fpga clock
    wire clk_0;
    wire clk_90;
    wire clk_180;
    wire clk_270;
    BUFG BUFG_clk0
       (.I(mmcm_clk_out_0),.O(clk_0));
    BUFG  BUFG_clk90
      (.I(mmcm_clk_out_90), .O(clk_90));
    BUFG BUFG_clk180
     (.I(mmcm_clk_out_180), .O(clk_180));
    BUFG BUFG_clk270
      (.I(mmcm_clk_out_270), .O(clk_270));

    assign adc_clk_out = clk_0;
    assign adc_clk90_out = clk_90;
    assign adc_clk180_out = clk_180;
    assign adc_clk270_out = clk_270;