Hi Mike, I have had a look at this. I can definitely tell you this is not a pipe-lining issue (as logic levels/interconnect = 3 stages, so no need to insert flip-flops to reduce the timing between the paths. It is difficult for me to analyse the path without seeing the floor plan, but I believe you will need to reduce the data path delay if you want to meet timing. The best is to open your design in the floor planner and highlight this failing path - hopefully you will see a long delay for the data path routing. It may be as easy as assigning an area constraint in your ucf file for the MAC itself, so that the data path is shorter by a few ns i.e. a pblock constraint.
I am not sure if you are using the CASPER_XPS tool flow at all or if you have your own flavour, but maybe there are existing constraints for the 1GbE that you could use? I am not sure if any of this helps, but it is a start anyway :). Kind regards, Adam On Fri, Sep 23, 2016 at 10:49 AM, Mike Movius <mi...@reutech.co.za> wrote: > > Hi All, > > I have a Roach2 design using the one_Gbe yellow block. I intermittently > have timing errors in this block seemingly unrelated to the design. Below > is a TS_mac_rx_clk timing constraint failure. The FPGA is running at 125 > MHz and approximately 50% of the resources are currently being utilized. > The design only sends data out of the interface. Any ideas on what is > causing this or how to fix it? > > > > ============================================================ > ==================== > > Timing constraint: TS_mac_rx_clk = PERIOD TIMEGRP "mac_rx_clk" 125 MHz > HIGH > > 50%; > > For more information, see Period Analysis in the Timing Closure User Guide > (UG612). > > > > 12625 paths analyzed, 2332 endpoints analyzed, 4 failing endpoints > > 4 timing errors detected. (4 setup errors, 0 hold errors, 0 component > switching limit errors) > > Minimum period is 8.157ns. > > ------------------------------------------------------------ > -------------------- > > Slack: -0.157ns (requirement - (data path - clock path > skew + uncertainty)) > > Source: fort_adm_rsp_bb_one_GbE/fort_ > adm_rsp_bb_one_GbE/enable_cpu_tx.cpu_buffer_tx/BU2/U0/blk_ > mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram > (RAM) > > Destination: temac_inst/temac_inst/emac_wrapper_inst/v6_emac > (CPU) > > Requirement: 8.000ns > > Data Path Delay: 7.893ns (Levels of Logic = 3) > > Clock Path Skew: -0.229ns (1.919 - 2.148) > > Source Clock: mac_mac_rx_clk rising at 0.000ns > > Destination Clock: mac_mac_rx_clk rising at 8.000ns > > Clock Uncertainty: 0.035ns > > > > Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE > > Total System Jitter (TSJ): 0.070ns > > Total Input Jitter (TIJ): 0.000ns > > Discrete Jitter (DJ): 0.000ns > > Phase Error (PE): 0.000ns > > > > Maximum Data Path at Slow Process Corner: fort_adm_rsp_bb_one_GbE/fort_ > adm_rsp_bb_one_GbE/enable_cpu_tx.cpu_buffer_tx/BU2/U0/blk_ > mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram > to temac_inst/temac_inst/emac_wrapper_inst/v6_emac > > Location Delay type Delay(ns) > Physical Resource > > > Logical Resource(s) > > --------------------------------------------------------------- > ------------------- > > RAMB36_X6Y36.DOBDO1 Trcko_DOB 2.073 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/enable_cpu_ > tx.cpu_buffer_tx/BU2/U0/blk_mem_generator/valid.cstr/ > ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram > > > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/enable_cpu_ > tx.cpu_buffer_tx/BU2/U0/blk_mem_generator/valid.cstr/ > ramloop[0].ram.r/v6_noinit.ram/TRUE_DP.SIMPLE_PRIM36.ram > > SLICE_X127Y181.C6 net (fanout=2) 1.727 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/cputx_tx_rd_data<1> > > SLICE_X127Y181.C Tilo 0.068 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>2 > > > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>2 > > SLICE_X127Y181.D3 net (fanout=1) 0.333 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>1 > > SLICE_X127Y181.D Tilo 0.068 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>2 > > > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>3 > > SLICE_X133Y180.D5 net (fanout=1) 0.719 > fort_adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_ > inst/mac_data_reg<1>2 > > SLICE_X133Y180.DMUX Tilo 0.191 > fort_adm_rsp_bb_one_GbE_app_dbg_data<0> > > fort_ > adm_rsp_bb_one_GbE/fort_adm_rsp_bb_one_GbE/gbe_tx_inst/mac_data_reg<1>4 > > TEMAC_X0Y1.CLIENTEMACTXD1 net (fanout=1) 2.527 > fort_adm_rsp_bb_one_GbE_app_dbg_data<1> > > TEMAC_X0Y1.CLIENTEMACTXCLIENTCLKIN Tmacdck_TXD 0.187 > temac_inst/temac_inst/emac_wrapper_inst/v6_emac > > > temac_inst/temac_inst/emac_wrapper_inst/v6_emac > > --------------------------------------------------------------- > --------------------------- > > Total 7.893ns > (2.587ns logic, 5.306ns route) > > > > > > > > > Please consider the environment before printing this e-mail > > View the Reutech Radar System online disclaimer at > http://www.rrs.co.za/links/E-maildisclaimer.asp > -- Adam Isaacson DBE: FPGA Engineer SKA-SA 3rd Floor The Park Park Road Pinelands 7405 Tel: +27215067300 (W) Fax: +27215067375 (W) Cell: +27825639602
