Hi Danny,
We are working on FPGA implementations of tunable fractional delay blocks based on Thiran IIR filters. They are very low complexity implementations. If you are interested, we will be happy to share. I CC'd my PhD student Viduneth who is working on Thiran based beamformers. Thanks, Arjuna Arjuna Madanayake Associate Professor ECE, University of Akron Tel: 330-972-8461 (W) 330-957-8704 (M) http://blogs.uakron.edu/aspc-lab http://blogs.uakron.edu/dharma "We wish to pursue the truth no matter where it leads; but to find the truth we need imagination and skepticism both. We will not be afraid to speculate, but we will be careful to distinguish speculation from fact. The Cosmos is full beyond measure of elegant truths, of exquisite interrelationships, of the awesome machinery of nature." - Carl Sagan ________________________________ From: [email protected] <[email protected]> on behalf of Daniel C Price <[email protected]> Sent: Wednesday, January 11, 2017 5:22 PM To: casper lists.berkeley.edu Subject: [casper] Programmable fractional delay block Hi all Does anyone have an implementation of a runtime-programmable fractional delay simulink block (e.g. 1/10th of a clock cycle) that they would be willing to share? Regards Danny -- Danny Price | [email protected]<mailto:[email protected]> | +1 617-386-3700
