Hi Franco, I don't know the low frequency limit, but for what it's worth, you could always run the adc at 320 MHz and just use 1 of the 8 outputs, which also has the benefit of avoiding and inter-core mismatch issues, since you'd effectively only be using 1 core. Or run faster and only use every Nth sample.
What error do you get when you clock below 600 MHz ADC clock? Cheers Jack On Mon, 3 Apr 2017, 19:22 Franco, <francocuro...@gmail.com> wrote: > Hi All, > > I'm working in an application where I need high frequency resolution > (~10kHz). For my model this means I need to run my ADC at ~40MHz (and the > FPGA at 5MHz). I'm not using an special memory block, just brams. I'm using > ROACH2, and ADC5G (https://casper.berkeley.edu/wiki/ADC1x5000-8). It is > possible to run the ADC at such low frequency? What is the minimum > acceptable frequency? I tried to find this information in the ADC > datasheet, but I haven't been successful. Also tried compiling simple > models at low frequencies, but everything below 600MHz failed. > > Thanks, > > Franco > > > > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
