Hi Mark,
I am glad you have sorted out the issue with the software registers and
snap shot blocks, so I won't comment here.
In terms of the version, I have this to day:
1) Please use the latest version of mlib_devel as the toolflow version
should now be 2.2.
2) The board on power up will load the multi-boot image on the FPGA. If you
read back the version number then you will get (0, 1, 2.2) - (0, 1, ..)
indicates multi-boot image and '2.2' indicates the major and minor version
number i.e. 'major version.minor version'). This number is 32 bits (2 MSB
bits represent the image type, 14 upper bits represent the major version,16
lower bits represents the minor version) If you program the fpg image i.e.
the toolflow image then you will read back the toolflfow image version,
which has been updated to 2.2 as well. The (0, 0,...) indicates that it is
a toolflow image, so it is correct and as expected. If anything goes wrong
with the uploading of the image then the board will load the golden image
(default/safe image) and when you read back the version then you will get
(1, 0, 2.2) where (1, 0,...) indicates the golden image.
The fpg file = the toolflow image. The version you read back depends on
which image is loaded on the FPGA. Casperfpga interfaces with the
microblaze running on the Virtex 7, which will read back the version number
stored in firmware depending on the image loaded on the FPGA.
I hope this clears things up.
Kind regards,
Adam
On Wed, Jun 28, 2017 at 9:29 PM, Peryer, Mark A. <
mark.per...@cfa.harvard.edu> wrote:
> In regards to the second question I asked in my previous email, I have
> solved the issue of being able to read the software registers and snapshot
> blocks. I needed to write the correct values to the software registers
> after programming in order to properly initialize the design.
>
> Thanks,
>
> Mark
>
> On Wed, Jun 28, 2017 at 12:33 PM, Peryer, Mark A. <
> mark.per...@cfa.harvard.edu> wrote:
>
>> Hello,
>>
>> There still appears to be an issue with the firmware version loaded onto
>> the Virtex 7. As the image below shows, after a power cycle the SKARAB
>> boots from the "multi-boot" image. However, once the .fpg file is uploaded,
>> the Virtex 7 reverts back to using the toolflow image.
>>
>> Additionally, I have been having an issue reading the correct values
>> stored in software registers and snapshot blocks in my JASPER design. Could
>> this be related to booting from the incorrect firmware image, or is it a
>> separate issue?
>>
>>
>> [image: Inline image 1]
>>
>> Thanks,
>>
>> Mark
>>
>> On Tue, Jun 27, 2017 at 11:04 AM, Clifford van Dyk <
>> cliffordvan...@gmail.com> wrote:
>>
>>> Excellent! Welcome to Skarab!
>>>
>>> Kind regards,
>>> Clifford
>>>
>>> On 6/27/2017 3:55 PM, Young, Andre wrote:
>>> > Hi Clifford, Adam
>>> >
>>> > Looks like it was the server NIC MTU size, I changed it from 1500 to
>>> > 9000 and then:
>>> >
>>> > # skarab-01
>>> > In [8]:
>>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-2
>>> 2_0944.fpg')
>>> > Out[8]: True
>>> >
>>> > # skarab-02
>>> > In [10]:
>>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-2
>>> 2_0944.fpg')
>>> > Out[10]: True
>>> >
>>> > Issue with golden image boot noted, we'll continue to look at that.
>>> >
>>> > Thanks very much,
>>> > André
>>> >
>>>
>>>
>>
>
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*Adam Isaacson*
FPGA Engineer
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