Hi All, I've been trying to get the DRAM to work on the ROACH2 and It looks like my data is getting jumbled when read out. I have a few questions I'm hoping people may have answers to.
1) If the roach2 clock, coming from adc0, is set to 200MHZ, do I need to set the DRAM data path clock rate to 200MHZ? Is it possible to set the DRAM data path clock rate higher in an attempt to use the asynchronous fifo and avoid readout issues? 2) Are the options, such as use BRAM fifos and Include CPU Interface implemented? I'm not sure what I want to use for the BRAM fifo setting. 3) Is it possible to ensure no CPU interface is made? I am not sure if the empty check box in the yellow block is doing this. 4) I noticed that https://github.com/argonnexraydetector/RoachFirmPy counts by 8 instead of 1 in the address field. I've been counting by 1, is that wrong? 5) Do I need to be making use of the rdack input? 6) Should I be using the ska-ka or casper_astro mlib_devel? I'm currently using casper_astro. I appreciate thoughts on any of these issues, either by themselves or as a whole. Application: I'm trying to buffer a 128 bit bus, for 800k clock cycles at 200MHZ and then stream it out over 10gbe UDP at a reasonable bitrate. If anyone has a similar design that works I'd be interested in taking a look. Thanks, --Adam ---------------------------------------------------- Adam Schoenwald - Electrical Engineer ---------------------------------------------------- -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.