Dear All, I am trying to compile design with the iADC and asiaa adc5g for ROACH2. Is it possible to feed both ADCs separate clocks and derive the fpga clock from one of the adc clocks ?
When I tried to compile a small design, I got "address overlap error": **** ERROR:EDK - INST:opb_adc5g_controller_0 BASEADDR HIGHADDR:0x00020000-0x0002ffff and INST:opb_adccontroller_0 BASEADDR-HIGHADDR:0x00020000-0x0002ffff - address space overlap! ***** Regards, Amit -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
