hi xavier, there's an ols tool flow that converts casper simulink to HDL to asic. we have used this flow a couple of times to develop asics, first designing in simulink, then test the design on a casper fpga board, and then compiling the HDL that simulink generates to an asic design.
see for example these two references: A 1.5GS/s 4096-Point Digital Spectrum Analyzer for Space-Borne Applications <http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/1090.html>, Brian Richards, Nicola Nicolici, Henry Chen, Kevin Chao, Robert Abiad, Dan Werthimer, Borivoje Nikolic, IEEE Custom Integrated Circuits Conference, 2009 http://ieeexplore.ieee.org/document/5280793/?reload=true D. Markovic, C. Chang, B. Richards, H. So, et al., "ASIC Design and Verification in an FPGA Environment," Proceedings Custom Integrated Circuits Conference (CICC'07), pp. 737-740, Sept 16-19, 2007, San Jose, CA. View Article <http://ieeexplore.ieee.org/document/4405836>Full Text: PDF <http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4405836>(450KB) but we don't use this tool flow anymore (it's about 10 years old and no longer used). instead we are using chisel for digital asic design. best wishes, dan On Thu, Aug 31, 2017 at 9:30 AM, Xavier Bosch <bruixa.aburrid...@gmail.com> wrote: > Hi everyone, > I wonder if there is any way/tool to port a CASPER/JASPER design to ASIC. > If the answer is no, is there any future plans for that? > thank you, > XB > > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To post to this group, send email to casper@lists.berkeley.edu.
