Hi All:
I bumped into 43 warnings and 7 errors when compiling
tutorials_devel/vivado/snap/tut_corr
<https://github.com/casper-astro/tutorials_devel/commit/55747cd737b1f7ab1c5ce06da58ad8e1f9f77f3c>
with
my 12-bit resolution snapadc. The output bitwidth of snapadc is actually 16
bit. Before running jasper I changed the output bitwidth of bus_expend and
input bitwidth of pfb_fir_generic to 16 bit.
May I ask for some advice on the correlator:
What parameters else should be changed?
Is it possible that the 12-bit resolution (16-bit bitwidth) data being
clipped or truncated in the correlator?
Is there a set of python modules for operating the correlator?
The warnings and errors report is attached for your reference.
Thank you very much!
Best,
Tian Huang
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=== Update Diagram (Elapsed: 5:17 min) ===
Warning:Output port 2 of 'snap_tut_corr/dir_x0/aa/cmult_dsp48e' is not
connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/ab/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/ab/real' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/ac/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/ac/real' is not connected.
Warning:Output port 2 of 'snap_tut_corr/dir_x0/bb/cmult_dsp48e' is not
connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/bc/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x0/bc/real' is not connected.
Warning:Output port 2 of 'snap_tut_corr/dir_x0/cc/cmult_dsp48e' is not
connected.
Warning:Output port 2 of 'snap_tut_corr/dir_x1/aa/cmult_dsp48e' is not
connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/ab/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/ab/real' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/ac/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/ac/real' is not connected.
Warning:Output port 2 of 'snap_tut_corr/dir_x1/bb/cmult_dsp48e' is not
connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/bc/imag' is not connected.
Warning:Output port 1 of 'snap_tut_corr/dir_x1/bc/real' is not connected.
Warning:Output port 2 of 'snap_tut_corr/dir_x1/cc/cmult_dsp48e' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree0' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree1' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree10' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree11' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree2' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree3' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree4' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree5' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree6' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree7' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree8' is not
connected.
Warning:Output port 1 of
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/bus_adder_tree/add_tree9' is not
connected.
Warning:Input port 1 of 'snap_tut_corr/pps_in' is not connected.
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dina/slice1'
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dina/slice2'
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dina/slice3'
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dinb/slice1'
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dinb/slice2'
Error:Slice endpoints must lie between the LSB and MSB
Error occurred during "Rate and Type Error Checking".
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dinb/slice3'
Error:A summary of Sysgen errors has been written to
'/home/ian/tutorials_devel/vivado/snap/ian_corr/snap_tut_corr_sysgen_error.log'
Reported by:
'snap_tut_corr/pfb_fir_generic/pfb_fir_taps/tap_delays/debus_dina/slice1'
Warning:Input port 1 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 2 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 3 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 4 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 5 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 6 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 7 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 8 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 9 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 10 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 11 of 'snap_tut_corr/snap_adc' is not connected.
Warning:Input port 12 of 'snap_tut_corr/snap_adc' is not connected.
