Hi Raoul -- will do. Just a reminder, in case people aren't doing it intentionally -- when you hit reply, your mail goes to the whole list!
Cheers Jack On Thu, 7 Dec 2017 at 09:25 Raoul Tawel <[email protected]> wrote: > Hi Jack, > > Can you please put my name down for your items #2 (Developing HDL cores – > i.e. JESD204B interface..) and #3 (testing new hardware). I would be > interested in the “ working remotely” option below. > > Thanks > > Raoul > > > > > > *From:* Jack Hickish [mailto:[email protected]] > *Sent:* Tuesday, December 05, 2017 10:43 AM > > > *To:* [email protected] > *Subject:* [casper] Berkeley CASPER group > > > > Hi CASPERites, > > > > Here at UC Berkeley we are in the process of putting together some job > adverts for CASPER research positions at UC Berkeley. We are hoping to > advertise positions for those with batchelors, masters, or doctoral degrees > to help develop next-gen CASPER tools and software/hardware infrastructure. > If you are interested, please get in touch or and/or send a CV. > > > > We're still debating the specifics of the positions we're going to > advertise and the level at which we should target them. This call for > declarations of interest serves as preliminary research to help with these > decisions. Obviously if/when jobs are officially posted I will advertise > them here, and they will be posted on the official UC Berkeley listings. > > > > Also, if there are folks who would be interested in working remotely on > short-term, smaller, well-defined deliverables, I suspect some of our goals > might suit this paradigm, so I'd be interested to hear from you, also. > > > > Here's a preliminary description of the work: > > > > The job responsibilities: > > > > -- Developing the python-based toolflow backend > > -- Developing new HDL cores (100 Gb Ethernet, JESD204 ADC interfaces, > memory controllers, etc.) > > -- Testing / bringing up new hardware (VCU118 Virtex Ultrascale+ board, > ADCs, other new boards) > > -- Developing embedded CPU (Microblaze) code for facilitating FPGA control > / monitoring > > -- Designing test benches / verification frameworks for libraries > > -- Porting DSP libraries out of Simulink, to a lower-level language > > -- Documenting the toolflow, DSP modules, and design practices of CASPER > > -- Website development, wiki/github curation. > > > > Desirable Skills: > > > > -- Competency with linux-based operating systems > > -- Experience with git > > -- Software languages: Python, C > > -- Hardware Description Languages: Verilog, VHDL, Simulink > > -- Experience with the CASPER toolflow > > -- Experience with Xilinx FPGAs > > -- Familiarity with high speed networking > > > > Please do get in touch if this sounds like it may be of interest! > > > > Cheers > > > > Jack > > -- > > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected].
