So updating the diagram at the moment produces no error, and you can see
the datatypes on the wires?


On Tue, Jan 30, 2018 at 9:49 AM, Bela Dixit <[email protected]> wrote:

> hie James,
>   I was getting some errors related to block, I corrected that error.
> After that it was proceeding but while synthesizing it stuck.
>
>
> Thanks & Regards,
> Bela
>
> Bela Dixit
> Electronics and Telecommunication engg(digital system)
>
>
> On Tue, Jan 30, 2018 at 1:07 PM, James Smith <[email protected]> wrote:
>
>> Hello Bela,
>>
>> That is a bit long - what happens if you just do Ctrl+D? Does it return
>> any messages?
>>
>> I also find that on Simulink if you select *Display -> Signals & Ports
>> -> Port Data Types *it produces a more useful result.
>>
>> Regards,
>> James
>>
>>
>> On Tue, Jan 30, 2018 at 9:33 AM, Bela Dixit <[email protected]> wrote:
>>
>>> Hie James,
>>>
>>>     I have waited around 7 to 9 hours, still I am getting same warnings.
>>>
>>> Thanks & Regards,
>>> Bela
>>>
>>>
>>> On Tue, Jan 30, 2018 at 12:22 PM, James Smith <[email protected]> wrote:
>>>
>>>> Hello Bela,
>>>>
>>>> That looks fine - there are normally lots of warnings. You just need to
>>>> wait, these compiles can take several hours sometimes depending on their
>>>> complexity. Average for mine have been 1.5-2 hours.
>>>>
>>>> Regards,
>>>> James
>>>>
>>>>
>>>> On Tue, Jan 30, 2018 at 8:48 AM, Bela Dixit <[email protected]>
>>>> wrote:
>>>>
>>>>> Thanks Andrew and James for suggestion.
>>>>> I had  updated the casper block by ctrl-D. Compilation proceed but
>>>>> still there is some problem in synthesis part.
>>>>> Kindly help me to sort out this problem.
>>>>> Please find the attached snapshot of command window.
>>>>> Thanks & Regards,
>>>>> Bela
>>>>>
>>>>>>
>>>>>>> On Thu, Jan 18, 2018 at 12:34 PM, James Smith <[email protected]>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> Hello Bela,
>>>>>>>>
>>>>>>>> I second Andrew's suggestion, but note also that "Error due to
>>>>>>>> multiple causes" can often mean that somewhere in the design there's a 
>>>>>>>> name
>>>>>>>> that Matlab doesn't like. Avoid using any capital letters or spaces in
>>>>>>>> block names, and avoid using names that are too long - if the full
>>>>>>>> file-path of the design contains capital letters, spaces or too many
>>>>>>>> characters (I think 64 is the limit?) then it can fail.
>>>>>>>>
>>>>>>>> Other Casperites can possibly correct me if I'm wrong on this but
>>>>>>>> this is the convention that I tend to follow.
>>>>>>>>
>>>>>>>> Regards,
>>>>>>>> James
>>>>>>>>
>>>>>>>>
>>>>>>>> On Thu, Jan 18, 2018 at 8:23 AM, Andrew Martens <[email protected]>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>>> Hi Bela
>>>>>>>>>
>>>>>>>>> Please open you design in Matlab/Simulink and then Press 'Ctrl-D'
>>>>>>>>> (hold the Ctrl key down and hit the D key at the same time). This 
>>>>>>>>> will do
>>>>>>>>> an 'Update' on your design and will give more useful error messages.
>>>>>>>>>
>>>>>>>>> Regards
>>>>>>>>> Andrew
>>>>>>>>>
>>>>>>>>> On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit <[email protected]>
>>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>>> Hi CASPERites,
>>>>>>>>>>
>>>>>>>>>> I am working on 5Gsps and ROACH2 boards.
>>>>>>>>>> While compiling four element 300MHz bandwidth correlator design, I 
>>>>>>>>>> am facing some error.
>>>>>>>>>> Kindly help me to sort out that error.
>>>>>>>>>> Please find the attached snapshot of error.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Thanks & Regards,
>>>>>>>>>>
>>>>>>>>>> Bela Dixit
>>>>>>>>>>
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