Thank you Dan and Matt.
Let me think about it. Best, Arjuna Arjuna Madanayake Associate Professor ECE, University of Akron Tel: 330-957-8704 (M) blogs.uakron.edu/aspc-lab<http://blogs.uakron.edu/aspc-lab> blogs.uakron.edu/dharma<http://blogs.uakron.edu/dharma> "We wish to pursue the truth no matter where it leads but to find the truth we need imagination and skepticism both. We will not be afraid to speculate, but we will be careful to distinguish speculation from fact. The Cosmos is full beyond measure of elegant truths, of exquisite interrelationships, of the awesome machinery of nature.” - Carl Sagan ________________________________ From: Matt Dexter <mdex...@berkeley.edu> Sent: Thursday, March 22, 2018 11:44 AM To: CASPER Mailing List Subject: Re: [casper] Power consumption of 960 MHz ADC chip using Analog Devices HMCAD1511 Thanks Dan. I forgot about those very early and probably not entirely trustworthy measurements. Very glad those values include the major caveats that there was no analog input provided nor load on the ZDok+ (digital) outputs. The ADC ICs probably were not programmed and instead the default power on ADC IC settings were in use. Perhaps the most interesting of those measurements was the large current increase if the supplied clock rate was higher than the max allowed for the programmed mode (eg 1000MHz in 4 chan mode w/ clock/1 programmed). There were discussions of installing a ZDok+ breakout gizmo of some sort so the ADCx250-8 xyz board was fully connected to the ROACHn FPGA, for programming and consuming of the digital data, but current sense resistors or external power supplies were in the path (the + portion of the ZDok+ connector) to make detailed measurements. That was never done as far as I know. Matt On Wed, 21 Mar 2018, Dan Werthimer wrote: > Date: Wed, 21 Mar 2018 17:53:20 -0700 > From: Dan Werthimer <d...@ssl.berkeley.edu> > Reply-To: casper@lists.berkeley.edu > To: CASPER Mailing List <casper@lists.berkeley.edu> > Subject: Re: [casper] Power consumption of 960 MHz ADC chip using Analog > Devices HMCAD1511 > > > hi arjuna, > > some power measurements are on the wiki at: > https://casper.berkeley.edu/wiki/ADC16x250-8_RJ45_rev_1 > > > (measured by matt dexter) (from the wiki): > > * > + Power: > o Power is delivered via the ZDok+ connector. See below for more > information. > o As of 2012sep04 only 4 different boards have been measured on > the lab bench as standalone > entities. There were no analog inputs and the ZDok+ outputs > were also unconnected. > o The current drawn across these boards was within 3 % of each > other. > o 5.0 VDC @ about 0.25 Amps from the ZDoK+ connector to power a > linear regulator and in turn the > 3.3 VDC clock distribution IC. > o The current drawn from 5 V is pretty constant at 0.24 to 0.25 > Amps for test frequencies > from 30 to 1000 MHz. > o 2.5 VDC @ about 1.4 Amps from the ZDoK+ connector to power a > linear regulator and in turn the > 1.8 VDC ADC ICs. > o as discussed above, the current drawn will increase if the > clock frequency is significantly > faster than the limit for the x1, x2 or x4 mode of the ADC > ICs. For example, if the ADC IC > chips are in x4 mode but the clock frequence is 1000 MHz, or > 4x the max speed of 250 MHz, > the current will be about 2.0 Amps. > o The current drawn from 2.5 V varies with the operating > frequency. A sample of amps versus > frequencies in MHz is : 0.15 @ 30, 0.19 @ 60, 0.38 @ 90, 0.49 > @ 120, 0.61 @ 150, 0.80 @ > 200, 0.98 Amps at 250 MHz. > o 1.8 VDC @ about 0.58 Amps from the ZDok+ connector to power the > digital side of the ADC ICs. > o The current draw from 1.8 V varies with the operating > frequency. A sample of amps versus > frequencies in MHz is : 0.1 @ 30, 0.11 @ 60, 0.18 @ 90, 0.23 > @ 120, 0.27 @ 150, 0.33 @ 200, > 0.38 Amps at 250 MHz. > o 1.5 VDC @ about 0.01 Amps (estimated) from the 10x2 cable and > connector driven by the RoachN > digital I/O connector. 1.5V is the Roach2 logic level. > > > > On Wed, Mar 21, 2018 at 5:18 PM, Madanayake,Habarakada Liyanachchi > <arj...@uakron.edu> wrote: > > Casperites, > > > I am trying to figure out the total power consumption of a 16-input > 8-bit ADC board operating > in the 960 MHz sample rate mode. The chip used on this board is > > an Analog Devices HMCAD1511. There are four of these ADC chips on one > board. > > The data sheet mentions a total power consumption of about 710 mW. I > assume thats for full rate > sampling. Does anyone know how correct this is? Has the power > consumption ever been measured by > the CASPER community? I need the total power > > consumption of this ADC chip when operating at about 960 MHz sample > rate (single channel per > chip). Any ideas would be most helpful. > > > I need this information to compare the total power consumption of an > 8-beam elementwise digital > beamformer using this ADC in each channel with an analog 8-beam > beamformer in CMOS. > > > > Thank you > > Arjuna Madanayake > > > > > Arjuna Madanayake > Associate Professor > ECE, University of Akron > Tel: 330-957-8704 (M) > > blogs.uakron.edu/aspc-lab > blogs.uakron.edu/dharma > > "We wish to pursue the truth no matter where it leads but to find the truth > we need imagination and > skepticism both. We will not be afraid to speculate, but we will be careful > to distinguish > speculation from fact. The Cosmos is full beyond measure of elegant truths, > of exquisite > interrelationships, of the awesome machinery of nature.” - Carl Sagan > > > > ___________________________________________________________________________________________________________ > From: dan.werthi...@gmail.com <dan.werthi...@gmail.com> on behalf of Dan > Werthimer > <d...@ssl.berkeley.edu> > Sent: Tuesday, March 20, 2018 5:49 PM > To: CASPER Mailing List; Ben Mazin; Karl Warnick; Francois Kapp > Subject: [casper] Xilinx RFsoc eval board with eight 4Gsps 12 bit ADCs. > > dear casperites, (and ben, karl, francois, who expressed interest in > RFsoc) > > please don't drool or salivate too much, but below is a photo of Xilinx's > RFsoc eval board, > "available sometime around july". > > we should port jasper tool flow to this eval board. > > the board's ZU28DR FPGA has: > 8 4 GSps 12 bit ADCs (each adc has 4 GHz analog bandwidth) > 8 6.4Gsps 14 bit DACs > 4272 DSP slices > 60 Mbit memory (on the FPGA) > 16 32 Gbit transceivers > > > if you run the board's four zSFP connectors at 32 Gbit/sec, > > then the aggregate rate = 128 Gbit/sec. > > if you want lots more I/O, the samtec 320 pin LPA connectors work up to > 17GHz, 34 Gbit/sec, either > single ended or differential. > > > > > i have a telecon later this week with xilinx to try to learn more about RFsoc > and this board. > > if you have questions, please let me know, and i'll try to relay them. > > > here are a few questions i plan to ask: > > cost? > > availability? > > can we interleave a pair of 4 Gsps ADC's to get 8 Gsps? (since they have 4 > GHz bandwidth) > > can we externally clock the ADC's with different phases? > > how do we connect analog inputs and clocks? (via lpa connectors?) > > > > best wishes, > > > dan > > > > > > > > [IMAGE] > > > > > -- > You received this message because you are subscribed to the Google Groups > "casper@lists.berkeley.edu" > group. > To unsubscribe from this group and stop receiving emails from it, send an > email to > casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > > -- > You received this message because you are subscribed to the Google Groups > "casper@lists.berkeley.edu" > group. > To unsubscribe from this group and stop receiving emails from it, send an > email to > casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > > > -- > You received this message because you are subscribed to the Google Groups > "casper@lists.berkeley.edu" > group. > To unsubscribe from this group and stop receiving emails from it, send an > email to > casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. 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