On 04/19/2018 11:52 AM, Jack Hickish wrote:
Thinking about this a moment longer -- I don't think an incorrect clock phase will be related to reported board clock problems. You can completely mangle the clock phase wrt to data lines, and the FPGA should still correctly lock onto the clock and derive an appropriate rate. The only symptom will be corrupted ADC data transfer.
Well, I found the cause even if I don't understand it yet. Since I have two ROACHs running side-by-side under a common parent, each is running in its own thread. That is, my software is threaded, as well as the fpga in its own thread under corr launched from within my thread. This still works. But then I start up another thread from within my thread to handle writing to disk. Then est_brd_clk() goes bad. Perhaps some corr expert reading this will have an explanation.
I can probably fix it by making the disk writing thread separate from the ROACH control thread. We'll see.
Thanks for your help. Tom -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected].
