Thanks Dan! Much appreciated!

From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Thursday, April 25, 2019 9:51 AM
To: CASPER Mailing List <casper@lists.berkeley.edu>
Subject: [EXTERNAL] Re: [casper] 1-bit quantization using Xilinx transceivers


hi dave,

i don't know about using the SERDES as ADC's.

paul horowitz and andrew howard used the xilinx LVDS inputs as flash ADC 
comparators
sampling at about 1 Gsps, they built thousands of multilevel ADC's,
biasing one input of each comparator at different DC levels using a resistor 
divider chain.
they found the LVDS inputs have high bandwidth (but not nearly as high as the 
serdes inputs),
and they have have low offset and the offset is fairly stable with temperature.
i think this work is written up in a chapter in andrew howard's thesis.

best wishes,

dan




Dan Werthimer
Marilyn and Watson Alberts Chair
Astronomy Dept and Space Sciences Lab
University of California, Berkeley


On Thu, Apr 25, 2019 at 9:37 AM 'Hawkins, David W (334B)' via 
casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu> 
<casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu>> wrote:
Hi All,

Has anyone on the CASPER list investigated using the Xilinx transceivers as 
1-bit ADCs?

Transceiver receivers can be kept coherent to a reference clock by configuring 
the receiver clock-and-data-recovery unit not to recover the clock from the 
incoming data stream.

There are some people in the GPS section here at JPL that are interested in 
using the transceivers for 1-bit sampling of GPS signals. They were interested 
if there was any published literature on this. I have a vague recollection of a 
CASPER-related grad student investigating this … but do not recall his name … 
making it a little hard to use Google as a backup for my memory.

Thanks!
Regards,
Dave Hawkins.



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