Hello Casperites, Does any one had try to use the Vivado HLS inside the Simulink?
I build a simple test that pass the RTL synthesis and gives the same results in the co-simulation with the C testbench code. Then I export the RTL to the system generator and import the project using the vivado HLS block in simulink, using as path the solution directory. I discover that the Vivado 2019.2 version has some bugs and you must modify the auxiliary.xml file, because the HLS set all the ports as it has bool, so I change the data type in that file. Beside that I didnt made any change to the files provided by HLS. But when I try to compile the system using the jasper command it fails saying that I didn't declare an axi4lite register inside the HLS project (I am using the hls_stream library).. Does anybody face the same problem? Maybe I could have some problem with my HLS code, but now I am only looking if the combo HLS+SysGen in the casper toolflow works, so if someone had successfully import a HLS code is good starting point. In another related question, look in the Xilinx forum I found that the HLS 2015.4 supports exporting the RTL to the ISE SysGen .... Has anyone tried it already? -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/ddd5fe7d-36d4-4b16-b358-cf3bb4405d4c%40lists.berkeley.edu.
