Hi Colm,

Good to hear from you. All is well provided the circumstances, I hope the same 
for you.

There has been some good progress in getting the RFDC yellow block working, but 
it still isn’t finished. I have some models in the toolflow with different 
preset RFDC configurations that are able to hand the information correctly to 
the underlying Vivado IP. There are also things like the AXI-Lite interface 
that needs to be correctly integrated and I am working on learning how to do 
that right.

Best,

Mitch

On Jul 8, 2020, at 3:58 AM, Colm Bracken 
<[email protected]<mailto:[email protected]>> wrote:

Hi Mitch,

I hope you are well.

Did you eventually get the yellow block for ADCs working in the tool flow for 
the ZCU111?
We kinda parked our attempts, and moved to just working with the Xilinx tools 
for programming for the moment. But, ultimately, we still want to eventually 
implement the CASPER toolflow on our ZCU111 boards.

I hope to attend the next hardware porting workshop (when rescheduled), where 
maybe we can make some more progress.

Thanks,
Colm

On Tue, 7 Jul 2020 at 23:06, Mitchell Burnett 
<[email protected]<mailto:[email protected]>> wrote:
Hi Lawrence,

Were you able to get some form of linux running? If you were then the next step 
would be to install tcpborphserver from source. From there you can use the 
command line tcpborphserver or casperfpga to upload the casper generated .fpg 
file.

If you know how the tool flow generates its output products you could grab the 
project bitstream and program that to the devices over JTAG but you would still 
need something to peek and poke at the registers and things inside the design.

I am sorry, the documentation is very lacking with regard to the work done on 
the ZCU111 this is mostly my fault. Let me see what I can do to hopefully bring 
what has been done to a place that others can replicate easily…

Best,

Mitch

> On Jul 7, 2020, at 2:57 PM, Lawrence Shing 
> <[email protected]<mailto:[email protected]>> wrote:
>
> For the existing test_vcu111.slx model, how do you upload the fpga file after 
> it's been compiled?
>
> JTAG, TFTP, microsd, ssh?
>
> Lawrence
>
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